82NM10 Datasheet, PDF (519/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

EHCI Controller Registers (D29:F7)
16.1.3
PCICMD—PCI Command Register
(USB EHCI—D29:F7)
Address Offset: 0h4–05h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:11 Reserved
10 Interrupt Disable — R/W.
0 = The function is capable of generating interrupts.
1 = The function can not generate its interrupt to the interrupt controller.
Note that the corresponding Interrupt Status bit (D29:F7:06h, bit 3) is not affected by
the interrupt enable.
9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
8 SERR# Enable (SERR_EN) — R/W.
0 = Disables EHC’s capability to generate an SERR#.
1 = The Enhanced Host controller (EHC) is capable of generating (internally) SERR#
when it receive a completion status other than “successful” for one of its DMA-
initiated memory reads on DMI (and subsequently on its internal interface).
7 Wait Cycle Control (WCC) — RO. Hardwired to 0.
6 Parity Error Response (PER) — RO.
1 = EHCI Host Controller will check for correct parity and halt operation when bad
parity is detected during the data phase as recommended by the EHCI
specification. If it detects bad parity on the address or command phases when this
bit is set to 1, the host controller does not take the cycle, halts the host controller
(if currently not halted), and sets the host system error bit in the USBSTS register.
Note that this applies to both requests and completions from the system interface.
This bit must be set in order for the parity errors to generate SERR#.
5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.
4 Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
3 Special Cycle Enable (SCE) — RO. Hardwired to 0.
2 Bus Master Enable (BME) — R/W.
0 = Disables this functionality.
1 = Enables the Chipset to act as a master on the PCI bus for USB transfers.
1 Memory Space Enable (MSE) — R/W. This bit controls access to the USB 2.0 Memory
Space registers.
0 = Disables this functionality.
1 = Enables accesses to the USB 2.0 registers. The Base Address register
(D29:F7:10h) for USB 2.0 should be programmed before this bit is set.
0 I/O Space Enable (IOSE) — RO. Hardwired to 0.
Datasheet
519