82NM10 Datasheet, PDF (4/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
PCI Express* Root Ports (D28:F0,F1,F2,F3)...........................................................81
5.2.1 Interrupt Generation ...............................................................................81
5.2.2 Power Management.................................................................................82
5.2.3 SERR# Generation ..................................................................................83
5.2.4 Hot-Plug ................................................................................................84
LAN Controller (B1:D8:F0) ..................................................................................86
5.3.1 LAN Controller PCI Bus Interface...............................................................86
5.3.2 Serial EEPROM Interface ..........................................................................91
5.3.3 CSMA/CD Unit ........................................................................................91
5.3.4 Media Management Interface ...................................................................92
5.3.5 TCO Functionality ...................................................................................92
Alert Standard Format (ASF) ...............................................................................94
5.4.1 ASF Management Solution Features/Capabilities .........................................95
5.4.2 ASF Hardware Support ............................................................................96
5.4.3 ASF Software Support .............................................................................97
LPC Bridge (w/ System and Management Functions) (D31:F0) .................................98
5.5.1 LPC Interface .........................................................................................98
5.5.2 SERR# Generation ................................................................................ 103
DMA Operation (D31:F0) .................................................................................. 104
5.6.1 Channel Priority.................................................................................... 105
5.6.2 Address Compatibility Mode ................................................................... 105
5.6.3 Summary of DMA Transfer Sizes ............................................................. 106
5.6.4 Autoinitialize ........................................................................................ 106
5.6.5 Software Commands ............................................................................. 107
LPC DMA ........................................................................................................ 107
5.7.1 Asserting DMA Requests ........................................................................ 107
5.7.2 Abandoning DMA Requests..................................................................... 108
5.7.3 General Flow of DMA Transfers ............................................................... 108
5.7.4 Terminal Count..................................................................................... 109
5.7.5 Verify Mode ......................................................................................... 109
5.7.6 DMA Request Deassertion ...................................................................... 109
5.7.7 SYNC Field / LDRQ# Rules ..................................................................... 110
8254 Timers (D31:F0) ...................................................................................... 111
5.8.1 Timer Programming .............................................................................. 112
5.8.2 Reading from the Interval Timer ............................................................. 113
8259 Interrupt Controllers (PIC) (D31:F0)........................................................... 114
5.9.1 Interrupt Handling ................................................................................ 116
5.9.2 Initialization Command Words (ICWx) ..................................................... 117
5.9.3 Operation Command Words (OCW) ......................................................... 118
5.9.4 Modes of Operation ............................................................................... 118
5.9.5 Masking Interrupts................................................................................ 121
5.9.6 Steering PCI Interrupts.......................................................................... 121
Advanced Programmable Interrupt Controller (APIC) (D31:F0)............................... 122
5.10.1 Interrupt Handling ................................................................................ 122
5.10.2 Interrupt Mapping................................................................................. 122
5.10.3 PCI / PCI Express* Message-Based Interrupts .......................................... 123
5.10.4 Front Side Bus Interrupt Delivery ............................................................ 124
Serial Interrupt (D31:F0) .................................................................................. 126
5.11.1 Start Frame ......................................................................................... 126
5.11.2 Data Frames ........................................................................................ 126
5.11.3 Stop Frame.......................................................................................... 127
5.11.4 Specific Interrupts Not Supported via SERIRQ........................................... 127
5.11.5 Data Frame Format............................................................................... 127
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