82NM10 Datasheet, PDF (147/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.14.7.5
Note:
Sx-G3-Sx, Handling Power Failures
Depending on when the power failure occurs and how the system is designed, different
transitions could occur due to a power failure.
The AFTER_G3 bit provides the ability to program whether or not the system should
boot once power returns after a power loss event. If the policy is to not boot, the
system remains in an S5 state (unless previously in S4). There are only three possible
events that will wake the system after a power failure.
1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low
(G3 state), the PWRBTN_STS bit is reset. When Chipset exits G3 after power
returns (RSMRST# goes high), the PWRBTN# signal is already high (because V_CC-
standby goes high before RSMRST# goes high) and the PWRBTN_STS bit is 0.
2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a
wake event, it is important to keep this signal powered during the power loss
event. If this signal goes low (active), when power returns the RI_STS bit is set and
the system interprets that as a wake event.
3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss.
Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.
Chipset monitors both PWROK and RSMRST# to detect for power failures. If PWROK
goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.
Although PME_EN is in the RTC well, this signal cannot wake the system after a power
loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#.
Table 5-61.Transitions Due to Power Failure
State at Power Failure AFTERG3_EN bit
S0, S1, S3
1
0
S4
1
0
S5
1
0
Transition When Power Returns
S5
S0
S4
S0
S5
S0
5.14.8
5.14.8.1
Thermal Management
Chipset has mechanisms to assist with managing thermal problems in the system.
THRM# Signal
The THRM# signal is used as a status input for a thermal sensor. Based on the THRM#
signal going active, Chipset generates an SMI# or SCI (depending on SCI_EN).
Datasheet
147