82NM10 Datasheet, PDF (532/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

EHCI Controller Registers (D29:F7)
Bit
Description
3 SMI on Periodic Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on Periodic is 1, then the host controller will
issue an SMI.
2 SMI on CF Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on CF is 1, then the host controller will issue an
SMI.
1 SMI on HCHalted Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1 and SMI on HCHalted is 1, then the host controller will
issue an SMI.
0 SMI on HCReset Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1 and SMI on HCReset is 1, then host controller will issue
an SMI.
16.1.29 ACCESS_CNTL—Access Control Register
(USB EHCI—D29:F7)
Address Offset: 80h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:1 Reserved
0 WRT_RDONLY — R/W. When set to 1, this bit enables a select group of normally read-
only registers in the EHC function to be written by software. Registers that may only be
written when this mode is entered are noted in the summary tables and detailed
description as “Read/Write-Special”. The registers fall into two categories:
1.
System-configured parameters, and
2.
Status bits
16.2
Note:
Note:
Memory-Mapped I/O Registers
The EHCI memory-mapped I/O space is composed of two sets of registers: Capability
Registers and Operational Registers.
The Chipset EHCI controller will not accept memory transactions (neither reads nor
writes) as a target that are locked transactions. The locked transactions should not be
forwarded to PCI as the address space is known to be allocated to USB.
When the EHCI function is in the D3 PCI power state, accesses to the USB 2.0 memory
range are ignored and result a master abort. Similarly, if the Memory Space Enable
(MSE) bit (D29:F7:04h, bit 1) is not set in the Command register in configuration
space, the memory range will not be decoded by the Chipset enhanced host controller
(EHC). If the MSE bit is not set, then the Chipset must default to allowing any memory
accesses for the range specified in the BAR to go to PCI. This is because the range may
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