82NM10 Datasheet, PDF (646/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
19.1.45 SMSCS—SMI/SCI Status Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: DCh–DFh
Default Value: 00000000h
Attribute:
Size:
R/WC
32 bits
Bit
Description
31
30
29:5
4
3
2
1
0
Power Management SCI Status (PMCS) — R/WC.
0 = Interrupt Not needed.
1 = PME control logic needs to generate an interrupt, and this interrupt has been
routed to generate an SCI.
Hot Plug SCI Status (HPCS) — R/WC.
0 = Interrupt Not needed.
1 = Hot-Plug controller needs to generate an interrupt, and has this interrupt been
routed to generate an SCI.
Reserved
Hot Plug Link Active State Changed SMI Status (HPLAS) — R/WC.
0 = No change
1 = SLSTS.LASC (D28:F0/F1/F2/F3:5A, bit 8) transitioned from 0-to-1, and MPC.HPME
(D28:F0/F1/F2/F3:D8, bit 1) is set. When this bit is set, an SMI# will be generated.
Hot Plug Command Completed SMI Status (HPCCM) — R/WC.
0 = No change
1 = SLSTS.CC (D28:F0/F1/F2/F3/:5A, bit 4) transitioned from 0-to-1, and MPC.HPME
(D28:F0/F1/F2/F3:D8, bit 1) is set. When this bit is set, an SMI# will be generated.
Hot Plug Attention Button SMI Status (HPABM) — R/WC.
0 = No change
1 = SLSTS.ABP (D28:F0/F1/F2/F3:5A, bit 0) transitioned from 0-to-1, and MPC.HPME
(D28:F0/F1/F2/F3:D8, bit 1) is set. When this bit is set, an SMI# will be generated.
Hot Plug Presence Detect SMI Status (HPPDM) — R/WC.
0 = No change
1 = SLSTS.PDC (D28:F0/F1/F2/F3:5A, bit 3) transitions from 0-to-1, and MPC.HPME
(D28:F0/F1/F2/F3:D8, bit 1) is set. When this bit is set, an SMI# will be generated.
Power Management SMI Status (PMMS) — R/WC.
0 = No change
1 = RSTS.PS (D28:F0/F1/F2/F3:60, bit 16) transitions from 0-to-1, and MPC.PMME
(D28:F0/F1/F2/F3:D8, bit 1) is set.
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Datasheet