82NM10 Datasheet, PDF (625/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
Bit
12
11
10:9
8
7
6
5
4
3
2:0
Description
Received Target Abort (RTA) — R/WC.
0 = Root port has not received a completion with completer abort from the backbone.
1 = Root port received a completion with completer abort from the backbone.
Signaled Target Abort (STA) — R/WC.
0 = No target abort received.
1 = Root port forwarded a target abort received from the downstream device onto the
backbone.
DEVSEL# Timing Status (DEV_STS) — Reserved per the PCI Express* Base
Specification.
Master Data Parity Error Detected (DPED) — R/WC.
0 = No data parity error received.
1 = Root port received a completion with a data parity error on the backbone and
PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is set.
Fast Back to Back Capable (FB2BC) — Reserved per the PCI Express* Base
Specification.
Reserved
66 MHz Capable — Reserved per the PCI Express* Base Specification.
Capabilities List — RO. Hardwired to 1. Indicates the presence of a capabilities list.
Interrupt Status — RO. Indicates status of Hot-Plug and power management
interrupts on the root port that result in INTx# message generation.
0 = Interrupt is deasserted.
1 = Interrupt is asserted.
This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the
state of PCICMD.Interrupt Disable bit (D28:F0/F1/F2/F3:04h:bit 10).
Reserved
19.1.5
19.1.6
RID—Revision Identification Register
(PCI Express—D28:F0/F1/F2/F3)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
Bit
7:0 Revision ID — RO.
Description
RO
8 bits
PI—Programming Interface Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 09h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Programming Interface — RO.
00h = No specific register level programming interface defined.
Datasheet
625