82NM10 Datasheet, PDF (124/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.11
Serial Interrupt (D31:F0)
Chipset supports a serial IRQ scheme. This allows a single signal to be used to report
interrupt requests. The signal used to transmit this information is shared between the
host, Chipset, and all peripherals that support serial interrupts. The signal line,
SERIRQ, is synchronous to PCI clock, and follows the sustained tri-state protocol that is
used by all PCI signals. This means that if a device has driven SERIRQ low, it will first
drive it high synchronous to PCI clock and release it the following PCI clock. The serial
IRQ protocol defines this sustained tri-state signaling in the following fashion:
• S – Sample Phase. Signal driven low
• R – Recovery Phase. Signal driven high
• T – Turn-around Phase. Signal released
Chipset supports a message for 21 serial interrupts. These represent the 15 ISA
interrupts (IRQ0–1, 2–15), the four PCI interrupts, and the control signals SMI# and
IOCHK#. The serial IRQ protocol does not support the additional APIC interrupts
(20–23).
5.11.1
Start Frame
The serial IRQ protocol has two modes of operation which affect the start frame. These
two modes are: Continuous, where Chipset is solely responsible for generating the start
frame; and Quiet, where a serial IRQ peripheral is responsible for beginning the start
frame.
The mode that must first be entered when enabling the serial IRQ protocol is
continuous mode. In this mode, Chipset asserts the start frame. This start frame is 4,
6, or 8 PCI clocks wide based upon the Serial IRQ Control Register, bits 1:0 at 64h in
Device 31:Function 0 configuration space. This is a polling mode.
When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the
SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a
peripheral drives the SERIRQ signal low. Chipset senses the line low and continues to
drive it low for the remainder of the Start Frame. Since the first PCI clock of the start
frame was driven by the peripheral in this mode, Chipset drives the SERIRQ line low for
1 PCI clock less than in continuous mode. This mode of operation allows for a quiet,
and therefore lower power, operation.
5.11.2
Data Frames
Once the Start frame has been initiated, all of the SERIRQ peripherals must start
counting frames based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has
exactly 3 phases of 1 clock each:
• Sample Phase. During this phase, the SERIRQ device drives SERIRQ low if the
corresponding interrupt signal is low. If the corresponding interrupt is high, then
the SERIRQ devices tri-state the SERIRQ signal. The SERIRQ line remains high due
to pull-up resistors (there is no internal pull-up resistor on this signal, an external
124
Datasheet