82NM10 Datasheet, PDF (162/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
occurring. The heartbeat messages are sent every 30 to 32 seconds. When an event
occurs, Chipset sends a new message and increments the SEQ[3:0] field. For heartbeat
messages, the sequence number does not increment.
The following rules/steps apply if the system is in a G0 state and the policy is for
Chipset to reboot the system after a hardware lockup:
1. On detecting the lockup, the SECOND_TO_STS bit is set. Chipset may send up to 1
Event message to the LAN controller. Chipset then attempts to reboot the
processor.
2. If the reboot at step 1 is successful then the BIOS should clear the
SECOND_TO_STS bit. This prevents any further Heartbeats from being sent. The
BIOS may then perform addition recovery/boot steps. (See note 2, below.)
3. If the reboot attempt in step 1 is not successful, the timer will timeout a third time.
At this point the system has locked up and was unsuccessful in rebooting. Chipset
does not attempt to automatically reboot again. Chipset starts sending a message
every heartbeat period
(30–32 seconds). The heartbeats continue until some external intervention occurs
(reset, power failure, etc.).
4. After step 3 (unsuccessful reboot after third timeout), if the user does a Power
Button Override, the system goes to an S5 state. Chipset continues sending the
messages every heartbeat period.
5. After step 4 (power button override after unsuccessful reboot) if the user presses
the Power Button again, the system should wake to an S0 state and the processor
should start executing the BIOS.
6. If step 5 (power button press) is successful in waking the system, Chipset
continues sending messages every heartbeat period until the BIOS clears the
SECOND_TO_STS bit. (See note 2)
7. If step 5 (power button press) is unsuccessful in waking the system, Chipset
continues sending a message every heartbeat period. Chipset does not attempt to
automatically reboot again. Chipset starts sending a message every heartbeat
period (30–32 seconds). The heartbeats continue until some external intervention
occurs (reset, power failure, etc.).
(See note 3)
8. After step 3 (unsuccessful reboot after third timeout), if a reset is attempted (using
a button that pulses PWROK low or via the message on the SMBus slave I/F),
Chipset attempts to reset the system.
9. After step 8 (reset attempt) if the reset is successful, the BIOS is run. Chipset
continues sending a message every heartbeat period until the BIOS clears the
SECOND_TO_STS bit. (See note 2)
10. After step 8 (reset attempt), if the reset is unsuccessful, Chipset continues sending
a message every heartbeat period. Chipset does not attempt to reboot the system
again without external intervention. (See note 3)
The following rules/steps apply if the system is in a G0 state and the policy is for
Chipset to not reboot the system after a hardware lockup.
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Datasheet