82NM10 Datasheet, PDF (600/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
18.2.8
18.2.9
STATESTS—State Change Status Register
(Intel HD Audio Controller—D27:F0)
Memory Address:HDBAR + 0Eh
Attribute:
R/WC
Default Value:
0000hSize:16 bits
Bit
Description
15:3
2:0
Reserved.
SDIN State Change Status Flags — R/WC. Flag bits that indicate which SDI signal(s)
received a state change event. The bits are cleared by writing 1’s to them.
Bit 0 = SDI0
Bit 1 = SDI1
Bit 2 = SDI2
NOTE: These bits are in the resume well and only cleared on a power on reset.
Software must not make assumptions about the reset state of these bits and
must set them appropriately.
GSTS—Global Status Register
(Intel HD Audio Controller—D27:F0)
Memory Address:HDBAR + 10h
Attribute:
R/WC
Default Value:
0000hSize:16 bits
Bit
Description
15:2
1
Reserved.
Flush Status — R/WC.
0 = Flush not completed
1 = This bit is set to 1 by hardware to indicate that the flush cycle initiated when the
Flush Control bit (HDBAR + 08h, bit 1) was set has completed.
NOTE: Software must write a 1 to clear this bit before the next time the Flush Control
bit is set to clear the bit.
0
Reserved.
600
Datasheet