82NM10 Datasheet, PDF (340/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI-to-PCI Bridge Registers (D30:F0)
Table 12-118.PCI Bridge Register Address Map (PCI-PCI—D30:F0) (Sheet 2 of 2)
Offset
4Ch-4Fh
50–51h
54h-57h
Mnemonic
BPC
SVCAP
SVID
Register Name
Default
Bridge Policy Configuration
Subsystem Vendor Capability Pointer
Subsystem Vendor IDs
00001200h
000Dh
00000000
Type
R/W RO
RO
R/WO
12.1.1
12.1.2
12.1.3
VID— Vendor Identification Register (PCI-PCI—D30:F0)
Offset Address: 00h–01h
Default Value: 8086h
Attribute:
Size:
RO
16 bits
Bit
15:0
Description
Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h.
DID— Device Identification Register (PCI-PCI—D30:F0)
Offset Address: 02h–03h
Default Value: See bit description
Attribute:
Size:
RO
16 bits
Bit
15:0
Description
Device ID — RO.This is a 16-bit value assigned to the PCI bridge. Refer to the
Intel^® I/O Controller Hub 7 Family Specification Update for the value of the Device ID
Register.
PCICMD—PCI Command (PCI-PCI—D30:F0)
Offset Address: 04h–05h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:11
10
9
8
7
6
5
Reserved
Interrupt Disable (ID) — RO. Hardwired to 0. The PCI bridge has no interrupts to
disable
Fast Back to Back Enable (FBE) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a.
SERR# Enable (SERR_EN) — R/W.
0 = Disable.
1 = Enable the Chipset to generate an NMI (or SMI# if NMI routed to SMI#) when the
D30:F0 SSE bit (offset 06h, bit 14) is set.
Wait Cycle Control (WCC) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a.
Parity Error Response (PER) — R/W.
0 = The Chipset ignores parity errors on the PCI bridge.
1 = The Chipset will set the SSE bit (D30:F0, offset 06h, bit 14) when parity errors are
detected on the PCI bridge.
VGA Palette Snoop (VPS) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a.
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Datasheet