82NM10 Datasheet, PDF (308/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
11.1.20 CAP_ID — Capability Identification Register
(LAN Controller—B1:D8:F0)
Offset Address: DCh
Default Value: 01h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Capability ID (CAP_ID) — RO. Hardwired to 01h to indicate that the chipset’s
integrated LAN controller supports PCI power management.
11.1.21 NXT_PTR — Next Item Pointer
(LAN Controller—B1:D8:F0)
Offset Address: DDh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Next Item Pointer (NXT_PTR) — RO. Hardwired to 00b to indicate that power
management is the last item in the capabilities list.
11.1.22 PM_CAP — Power Management Capabilities
(LAN Controller—B1:D8:F0)
Offset Address: DEh–DFh
Default Value: 7E21h
Attribute:
Size:
RO
16 bits
Bit
Description
15:11 PME Support (PME_SUP) — RO. Hardwired to 11111b. This 5-bit field indicates the
power states in which the LAN controller may assert PME#. The LAN controller
supports wake-up in all power states.
10 D2 Support (D2_SUP) — RO. Hardwired to 1 to indicate that the LAN controller
supports the D2 power state.
9 D1 Support (D1_SUP) — RO. Hardwired to 1 to indicate that the LAN controller
supports the D1 power state.
8:6 Auxiliary Current (AUX_CUR) — RO. Hardwired to 000b to indicate that the LAN
controller implements the Data registers. The auxiliary power consumption is the same
as the current consumption reported in the D3 state in the Data register.
5 Device Specific Initialization (DSI) — RO. Hardwired to 1 to indicate that special
initialization of this function is required (beyond the standard PCI configuration header)
before the generic class device driver is able to use it. DSI is required for the LAN
controller after D3-to-D0 reset.
4 Reserved
3 PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that the LAN controller does
not require a clock to generate a power management event.
2:0 Version (VER) — RO. Hardwired to 010b to indicate that the LAN controller complies
with of the PCI Power Management Specification, Revision 1.1.
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Datasheet