82NM10 Datasheet, PDF (181/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Table 5-73.USB Legacy Keyboard State Transitions (Sheet 1 of 2)
Current
State
Action
Data
Value
Next
State
Comment
IDLE
IDLE
IDLE
IDLE
IDLE
GateState1
GateState1
GateState1
GateState1
GateState1
GateState2
GateState2
64h / Write
64h / Write
64h / Read
60h / Write
60h / Read
60h / Write
64h / Write
64h / Write
60h / Read
64h / Read
64 / Write
64h / Write
D1h
Not D1h
N/A
Don't Care
N/A
XXh
D1h
Not D1h
N/A
N/A
FFh
Not FFh
GateState1 Standard D1 command. Cycle passed
through to 8042. SMI# doesn't go active.
PSTATE (offset C0, bit 6) goes to 1.
IDLE
Bit 3 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
IDLE
Bit 2 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
IDLE
Bit 1 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
IDLE
Bit 0 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
GateState2
Cycle passed through to 8042, even if trap
enabled in Bit 1 in Config Register. No SMI#
generated. PSTATE remains 1. If data value
is not DFh or DDh then the 8042 may chose
to ignore it.
GateState1
Cycle passed through to 8042, even if trap
enabled via Bit 3 in Config Register. No
SMI# generated. PSTATE remains 1. Stay
in GateState1 because this is part of the
double-trigger sequence.
ILDE
Bit 3 in Config space determines if cycle
passed through to 8042 and if SMI#
generated. PSTATE goes to 0. If Bit 7 in
Config Register is set, then SMI# should be
generated.
IDLE
This is an invalid sequence. Bit 0 in Config
Register determines if cycle passed through
to 8042 and if SMI# generated. PSTATE
goes to 0. If Bit 7 in Config Register is set,
then SMI# should be generated.
GateState1 Just stay in same state. Generate an SMI#
if enabled in Bit 2 of Config Register.
PSTATE remains 1.
IDLE
Standard end of sequence. Cycle passed
through to 8042. PSTATE goes to 0. Bit 7 in
Config Space determines if SMI# should be
generated.
IDLE
Improper end of sequence. Bit 3 in Config
Register determines if cycle passed through
to 8042 and if SMI# generated. PSTATE
goes to 0. If Bit 7 in Config Register is set,
then SMI# should be generated.
Datasheet
181