82NM10 Datasheet, PDF (562/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SMBus Controller Registers (D31:F3)
17.2.2
Note:
HST_CNT—Host Control Register (SMBUS—D31:F3)
Register Offset: SMBASE + 02h
Default Value: 00h
Attribute:
Size:
R/W, WO
8-bits
A read to this register will clear the byte pointer of the 32-byte buffer.
Bit
Description
7 PEC_EN — R/W.
0 = SMBus host controller does not perform the transaction with the PEC phase appended.
1 = Causes the host controller to perform the SMBus transaction with the Packet Error Checking phase
appended. For writes, the value of the PEC byte is transferred from the PEC Register. For reads, the
PEC byte is loaded in to the PEC Register. This bit must be written prior to the write in which the
START bit is set.
6 START — WO.
0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status register (offset 00h)
can be used to identify when the Chipset has finished the command.
1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All registers should
be setup prior to writing a 1 to this bit position.
5 LAST_BYTE — WO. This bit is used for Block Read commands.
1 = Software sets this bit to indicate that the next byte will be the last byte to be received for the
block. This causes the Chipset to send a NACK (instead of an ACK) after receiving the last byte.
NOTE: Once the SECOND_TO_STS bit in TCO2_STS register (D31:F0, TCOBASE+6h, bit 1) is set, the
LAST_BYTE bit also gets set. While the SECOND_TO_STS bit is set, the LAST_BYTE bit cannot
be cleared. This prevents the Chipset from running some of the SMBus commands (Block Read/
Write, I²C Read, Block I²C Write).
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