82NM10 Datasheet, PDF (304/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
11.1.8
CLS—Cache Line Size Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:5 Reserved
4:3 Cache Line Size (CLS) — R/W.
00 = Memory Write and Invalidate (MWI) command will not be used by the integrated
LAN controller.
01 = MWI command will be used with Cache Line Size set to 8 DWords (only set if a
value of 08h is written to this register).
10 = MWI command will be used with Cache Line Size set to 16 DWords (only set if a
value of 10h is written to this register).
11 = Invalid. MWI command will not be used.
2:0 Reserved
11.1.9
PMLT—Primary Master Latency Timer Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Dh
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:3 Master Latency Timer Count (MLTC) — R/W. This field defines the number of PCI
clock cycles that the integrated LAN controller may own the bus while acting as bus
master.
2:0 Reserved
11.1.10 HEADTYP—Header Type Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Eh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7 Multi-Function Device (MFD) — RO. Hardwired to 0 to indicate a single function
device.
6:0 Header Type (HTYPE) — RO. This 7-bit field identifies the header layout of the
configuration space as an Ethernet controller.
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