82NM10 Datasheet, PDF (349/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI-to-PCI Bridge Registers (D30:F0)
Bit
Description
9 Secondary Discard Timer (SDT) — R/W. This bit sets the maximum number of PCI
clock cycles that the Chipset waits for an initiator on PCI to repeat a delayed
transaction request. The counter starts once the delayed transaction data is has been
returned by the system and is in a buffer in the Chipset PCI bridge. If the master has
not repeated the transaction at least once before the counter expires, the Chipset PCI
bridge discards the transaction from its queue.
0 = The PCI master timeout value is between 2¹⁵ and 2¹⁶ PCI clocks
1 = The PCI master timeout value is between 2¹⁰ and 2¹¹ PCI clocks
8 Primary Discard Timer (PDT) — R/W. This bit is R/W for software compatibility only.
7 Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The PCI logic will not generate
fast back-to-back cycles on the PCI bus.
6 Secondary Bus Reset (SBR) — R/W. This bit controls PCIRST# assertion on PCI.
0 = Bridge de-asserts PCIRST#
1 = Bridge asserts PCIRST#. When PCIRST# is asserted, the delayed transaction
buffers, posting buffers, and the PCI bus are initialized back to reset conditions.
The rest of the part and the configuration registers are not affected.
5 Master Abort Mode (MAM) — R/W. This bit controls the Chipset PCI bridge’s
behavior when a master abort occurs:
Master Abort on (G)MCH or CPU/Chipset Interconnect (DMI):
0 = Bridge asserts TRDY# on PCI. It drives all 1’s for reads, and discards data on
writes.
1 = Bridge returns a target abort on PCI.
Master Abort PCI (non-locked cycles):
0 = Normal completion status will be returned on the (G)MCH or CPU/Chipset
interconnect.
1 = Target abort completion status will be returned on the (G)MCH or CPU/Chipset
interconnect.
NOTE: All locked reads will return a completer abort completion status on the (G)MCH
or CPU/Chipset interconnect.
4 VGA 16-Bit Decode (V16D) — R/W. This bit controls enables the Chipset PCI bridge
to provide 16-bits decoding of VGA I/O address precluding the decode of VGA alias
addresses every 1 KB. This bit requires the VGAE bit in this register be set.
3 VGA Enable (VGAE) — R/W. When set to a 1, the Chipset PCI bridge forwards the
following transactions to PCI regardless of the value of the I/O base and limit registers.
The transactions are qualified by CMD.MSE (D30:F0:04 bit 1) and CMD.IOSE
(D30:F0:04 bit 0) being set.
• Memory addresses: 000A0000h-000BFFFFh
• I/O addresses: 3B0h-3BBh and 3C0h-3DFh. For the I/O addresses, bits [63:16] of
the address must be 0, and bits [15:10] of the address are ignored (i.e., aliased).
The same holds true from secondary accesses to the primary interface in reverse. That
is, when the bit is 0, memory and I/O addresses on the secondary interface between
the above ranges will be claimed.
Datasheet
349