82NM10 Datasheet, PDF (240/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Electrical Characteristics
Table 8-105.Power Management Timings (Sheet 3 of 3)
Sym
Parameter
t295 SLP_S4# active to SLP_S5# active
Min
1
Max Units Notes
2
RTCCLK
4, 16
t296 Wake Event to SLP_S5# inactive
1
10 RTCCLK
4
t297 SLP_S5# inactive to SLP_S4# inactive
See Note Below
3
t298 SLP_S4# inactive to SLP_S3# inactive
1
2 RTCCLK
4
t299 S4 Wake Event to SLP_S4# inactive (S4
Wake)
See Note Below
3
t300 S3 Wake Event to SLP_S3# inactive (S3
Wake)
t301 CPUSLP# inactive to STPCLK# inactive
(Nettop Only)
t302 SLP_S3# inactive to Chipset check for
PWROK active
small
0
as
possi
RTCCLK
4
ble
8
PCICLK
4
5
msec
t303 SLP_S3# active to Vcc supplies inactive
5
Other Timings
t310 THRMTRIP# active to SLP_S3#, SLP_S4#,
SLP_S5# active
t311 RSMRST# rising edge transition from 20% to 80%
t312 RSMRST# falling edge transition
us
15, 17
3 PCI CLK
50
us
18
Fig
8-37
8-38
8-39
8-40
8-37
8-38
8-39
8-40
8-37
8-38
8-39
8-40
8-37
8-38
8-39
8-40
8-37
8-38
8-39
8-40
8-37
8-38
8-39
8-40
8-36
8-37
8-38
8-39
8-40
NOTES:
1.
If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up
together, the delay from RTCRST# and RSMRST# inactive to SUSCLK toggling may be as
much as 2.5 s.
2.
If the AFTERG3_EN bit (GEN_PMCON_3 Configuration Register Bit 1) is set to a 1,
SLP_S5# will not be de-asserted until a wake event is detected. If the AFTERG3_EN bit is
set to 0, SLP_S5# will deassert within the specification listed in the table.
3.
The Min/Max times depend on the programming of the “SLP_S4# Minimum Assertion
Width” and the “SLP_S4# Assertion Stretch Enable bits (D31:F0:A4h bits 5:3).
4.
These transitions are clocked off the internal RTC. 1 RTC clock is approximately 28.992 µs
to 32.044 µs.
240
Datasheet