82NM10 Datasheet, PDF (359/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.1.7
SCC—Sub Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Ah
Default Value: 01h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Sub Class Code — RO. 8-bit value that indicates the category of bridge for the LPC
bridge.
01h = PCI-to-ISA bridge.
13.1.8
BCC—Base Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Bh
Default Value: 06h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Base Class Code — RO. 8-bit value that indicates the type of device for the LPC
bridge.
06h = Bridge device.
13.1.9
PLT—Primary Latency Timer Register (LPC I/F—D31:F0)
Offset Address: 0Dh
Default Value: 00h
Attribute:
Size:
Bit
Description
7:3 Master Latency Count (MLC) — Reserved.
2:0 Reserved.
RO
8 bits
13.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0)
Offset Address: 0Eh
Default Value: 80h
Attribute:
Size:
RO
8 bits
Bit
Description
7 Multi-Function Device — RO. This bit is 1 to indicate a multi-function device.
6:0 Header Type — RO. This 7-bit field identifies the header layout of the configuration
space.
Datasheet
359