82NM10 Datasheet, PDF (489/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.1.34 PCS—Port Control and Status Register (SATA–D31:F2)
Address Offset: 92h–93h
Default Value: 0000h
Attribute:
Size:
R/W, R/WC, RO
16 bits
This register is only used in systems that do not support AHCI. In AHCI enabled
systems, bits[3:0] must always be set bits[2,0] and the status of the port is controlled
through AHCI memory space.
Bits
15:6
5
4
3:2
1
0
Description
Reserved.
Port 1 Present (P1P) — RO. The status of this bit may change at any time. This bit
is cleared when the port is disabled via P1E. This bit is not cleared upon surprise
removal of a device.
0 = No device detected.
1 = The presence of a device on Port 1 has been detected.
Port 0 Present (P0P) — RO. The status of this bit may change at any time. This bit
is cleared when the port is disabled via P0E. This bit is not cleared upon surprise
removal of a device.
0 = No device detected.
1 = The presence of a device on Port 0 has been detected.
Reserved.
Port 1 Enabled (P1E) — R/W.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
can detect devices.
NOTE: This bit takes precedence over P1CMD.SUD (offset ABAR+198h:bit 1)
Port 0 Enabled (P0E) — R/W.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
can detect devices.
NOTE: This bit takes precedence over P0CMD.SUD (offset ABAR+118h:bit 1)
Datasheet
489