82NM10 Datasheet, PDF (463/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

UHCI Controllers Registers
Bit
Description
4 Host Controller Process Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The host controller has detected a fatal error. This indicates that the host controller
suffered a consistency check failure while processing a Transfer Descriptor. An
example of a consistency check failure would be finding an invalid PID field while
processing the packet header portion of the TD. When this error occurs, the host
controller clears the Run/Stop bit in the Command register (D29:F0/F1/F2/
F3:BASE + 00h, bit 0) to prevent further schedule execution. A hardware interrupt
is generated to the system.
3 Host System Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = A serious error occurred during a host system access involving the host controller
module. In a PCI system, conditions that set this bit to 1 include PCI Parity error,
PCI Master Abort, and PCI Target Abort. When this error occurs, the host controller
clears the Run/Stop bit in the Command register to prevent further execution of
the scheduled TDs. A hardware interrupt is generated to the system.
2 Resume Detect (RSM_DET) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The host controller received a “RESUME” signal from a USB device. This is only
valid if the Host controller is in a global suspend state (Command register, D29:F0/
F1/F2/F3:BASE + 00h, bit 3 = 1).
1 USB Error Interrupt — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Completion of a USB transaction resulted in an error condition (e.g., error counter
underflow). If the TD on which the error interrupt occurred also had its IOC bit
(D29:F0/F1/F2/F3:BASE + 04h, bit 2) set, both this bit and Bit 0 are set.
0 USB Interrupt (USBINT) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The host controller sets this bit when the cause of an interrupt is a completion of a
USB transaction whose Transfer Descriptor had its IOC bit set. Also set when a
short packet is detected (actual length field in TD is less than maximum length field
in TD), and short packet detection is enabled in that TD.
14.2.3
USBINTR—USB Interrupt Enable Register
I/O Offset:
Base + (04h–05h)Attribute:R/W
Default Value:
0000hSize:16 bits
This register enables and disables reporting of the corresponding interrupt to the
software. When a bit is set and the corresponding interrupt is active, an interrupt is
generated to the host. Fatal errors (host controller processor error, (D29:F0/F1/F2/
F3:BASE + 02h, bit 4, USBSTS Register) cannot be disabled by the host controller.
Interrupt sources that are disabled in this register still appear in the Status Register to
allow the software to poll for events.
Datasheet
463