82NM10 Datasheet, PDF (283/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Chipset Configuration Registers
Bit
11:8
7:4
3:0
Description
SATA Pin (SIP) — R/W. This field indicates which pin the SATA controller drives as
its interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
Reserved
PCI Bridge Pin (PCIP) — RO. Currently, the PCI bridge does not generate an
interrupt, so this field is read-only and 0.
10.1.38 D30IP—Device 30 Interrupt Pin Register
Offset Address: 3104–3107h
Default Value: 00002100h
Attribute:
Size:
R/W, RO
32-bit
Bit
Description
31:4
3:0
Reserved
LPC Bridge Pin (LIP) — RO. Currently, the LPC bridge does not generate an
interrupt, so this field is read-only and 0.
10.1.39 D29IP—Device 29 Interrupt Pin Register
Offset Address: 3108–310Bh
Default Value: 10004321h
Attribute:
Size:
R/W
32-bit
Bit
Description
31:28
27:16
15:12
EHCI Pin (EIP) — R/W. This field indicates which pin the EHCI controller drives as
its interrupt.
0h = No interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
Reserved
UHCI #3 Pin (U3P) — R/W. This field indicates which pin the UHCI controller #3
(ports 6 and 7) drives as its interrupt.
0h = No interrupt
1h = INTA#
2h = INTB#
3h = INTC#
4h = INTD# (Default)
5h–Fh = Reserved
Datasheet
283