82NM10 Datasheet, PDF (294/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Chipset Configuration Registers
Bit
Description
9
Server Error Reporting Mode (SERM) — R/W.
0 = The Chipset is the final target of all errors. The (G)MCH/CPU sends a messages to the Chipset
for the purpose of generating NMI.
1 = The (G)MCH/CPU is the final target of all errors from PCI Express* and DMI. In this mode, if the
Chipset detects a fatal, non-fatal, or correctable error on DMI or its downstream ports, it sends
a message to the (G)MCH/CPU. If the Chipset receives an ERR_* message from the
downstream port, it sends that message to the (G)MCH/CPU.
8:7
Reserved
6
(Netbook
Only)
FERR# MUX Enable (FME) — R/W. This bit enables FERR# to be a processor break event
indication.
0 = Disabled.
1 = The Chipset examines FERR# during a C2, C3, or C4 state as a break event.
See Chapter 5.14.5 - Volume 1 for a functional description.
6
(Nettop
Only)
Reserved
5
No Reboot (NR) — R/W. This bit is set when the “No Reboot” strap (SPKR pin on Chipset) is
sampled high on PWROK. This bit may be set or cleared by software if the strap is sampled low but
may not override the strap when it indicates “No Reboot”.
0 = System will reboot upon the second timeout of the TCO timer.
1 = The TCO timer will count down and generate the SMI# on the first timeout, but will not reboot
on the second timeout.
4
Alternate Access Mode Enable (AME) — R/W.
0 = Disabled.
1 = Alternate access read only registers can be written, and write only registers can be read. Before
entering a low power state, several registers from powered down parts may need to be saved.
In the majority of cases, this is not an issue, as registers have read and write paths. However,
several of the ISA compatible registers are either read only or write only. To get data out of
write-only registers, and to restore data into read-only registers, the Chipset implements an
alternate access mode. For a list of these registers see Section 5.14.10.
3
Reserved.
2
Reserved Page Route (RPR) — R/W. This bit determines where to send the reserved page
registers. These addresses are sent to PCI or LPC for the purpose of generating POST codes. The I/
O addresses modified by this field are: 80h, 84h, 85h, 86h, 88h, 8Ch, 8Dh, and 8Eh.
0 = Writes will be forwarded to LPC, shadowed within the Chipset, and reads will be returned from
the internal shadow
1 = Writes will be forwarded to PCI, shadowed within the Chipset, and reads will be returned from
the internal shadow.
NOTE: If some writes are completed to LPC/PCI to these I/O ranges, and then this bit is flipped
such that writes will now go to the other interface, the reads will not return what was last
written. Shadowing is performed on each interface.
The aliases for these registers, at 90h, 94h, 95h, 96h, 98h, 9Ch, 9Dh, and 9Eh, are always decoded
to LPC.
1
Reserved
0
BIOS Interface Lock-Down (BILD) — R/WLO.
0 = Disabled.
1 = Prevents BUC.TS (offset 3414, bit 0) and GCS.BBS (offset 3410h, bits 11:10) from being
changed. This bit can only be written from 0 to 1 once.
294
Datasheet