82NM10 Datasheet, PDF (309/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
11.1.23 PMCSR — Power Management Control/
Status Register (LAN Controller—B1:D8:F0)
Offset Address: E0h–E1h
Default Value: 0000h
Attribute:
Size:
RO, R/W, R/WC
16 bits
Bit
Description
15 PME Status (PME_STAT) — R/WC.
0 = Software clears this bit by writing a 1 to it. This also deasserts the PME# signal and
clears the PME status bit in the Power Management Driver Register. When the
PME# signal is enabled, the PME# signal reflects the state of the PME status bit.
1 = Set upon occurrence of a wake-up event, independent of the state of the PME
enable bit.
14:13 Data Scale (DSCALE) — RO. This field indicates the data register scaling factor. It
equals 10b for registers 0 through 8 and 00b for registers nine through fifteen, as
selected by the “Data Select” field.
12:9 Data Select (DSEL) — R/W. This field is used to select which data is reported through
the Data register and Data Scale field.
8 PME Enable (PME_EN) — R/W. This bit enables the chipset’s integrated LAN
controller to assert PME#.
0 = The device will not assert PME#.
1 = Enable PME# assertion when PME Status is set.
7:5 Reserved
4 Dynamic Data (DYN_DAT) — RO. Hardwired to 0 to indicate that the device does
not support the ability to monitor the power consumption dynamically.
3:2 Reserved
1:0 Power State (PWR_ST) — R/W. This 2-bit field is used to determine the current
power state of the integrated LAN controller, and to put it into a new power state. The
definition of the field values is as follows:
00 = D0
01 = D1
10 = D2
11 = D3
Datasheet
309