82NM10 Datasheet, PDF (234/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Electrical Characteristics
Table 8-98.SATA Interface Timings
Sym
Parameter
t123 COMRESET
t124 COMWAKE transmit spacing
t125 OOB Operating Data period
Min
Max
310.4 329.6
103.5 109.9
646.67 686.67
Units
ns
ns
ns
Notes Figure
3
3
4
NOTES:
1.
20% – 80% at transmitter
2.
80% – 20% at transmitter
3.
As measured from 100 mV differential crosspoints of last and first edges of burst.
4.
Operating data period during Out-Of-Band burst transmissions.
Table 8-99.SMBus Timing
Sym
Parameter
t130 Bus Tree Time Between Stop and Start
Condition
t131 Hold Time after (repeated) Start Condition.
After this period, the first clock is
generated.
t132 Repeated Start Condition Setup Time
t133 Stop Condition Setup Time
t134 Data Hold Time
t135 Data Setup Time
t136 Device Time Out
t137 Cumulative Clock Low Extend Time (slave
device)
t138 Cumulative Clock Low Extend Time (master
device)
Min
4.7
4.0
4.7
4.0
0
250
25
—
—
Max
—
Units Notes Figure
µs
—
µs
—
µs
—
µs
—
ns
—
ns
35
ms
25
ms
10
ms
8-30
1
2
3
8-31
4
NOTES:
1.
t134 has a minimum timing for I²C of 0 ns, while the minimum timing for SMBus is 300 ns.
2.
A device will timeout when any clock low exceeds this value.
3.
t137 is the cumulative time a slave device is allowed to extend the clock cycles in one
message from the initial start to stop. If a slave device exceeds this time, it is expected to
release both its clock and data lines and reset itself.
4.
t138 is the cumulative time a master device is allowed to extend its clock cycles within
each byte of a message as defined from start-to-ack, ack-to-ack or ack-to-stop.
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Datasheet