82NM10 Datasheet, PDF (200/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Note:
This command is supported independent of the setting of the I2C_EN bit. The I²C Read
command with the PEC_EN bit set produces undefined results. Software must force
both the PEC_EN and AAC bit to 0 when running this command.
For I²C Read command, the value written into bit 0 of the Transmit Slave Address
Register (SMB I/O register, offset 04h) needs to be 0.
The format that is used for the command is shown in Table 5-76.
Table 5-76.I²C Block Read
Bit
Description
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
–
–
–
–
Start
Slave Address — 7 bits
Write
Acknowledge from slave
Send DATA1 register
Acknowledge from slave
Repeated Start
Slave Address — 7 bits
Read
Acknowledge from slave
Data byte 1 from slave — 8 bits
Acknowledge
Data byte 2 from slave — 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data byte N from slave — 8 bits
NOT Acknowledge
Stop
Chipset will continue reading data from the peripheral until the NAK is received.
Block Write–Block Read Process Call
The block write-block read process call is a two-part message. The call begins with a
slave address and a write condition. After the command code the host issues a write
byte count (M) that describes how many more bytes will be written in the first part of
the message. If a master has 6 bytes to send, the byte count field will have the value 6
(0000 0110b), followed by the 6 bytes of data. The write byte count (M) cannot be 0.
The second part of the message is a block of read data beginning with a repeated start
condition followed by the slave address and a Read bit. The next byte is the read byte
count (N), which may differ from the write byte count (M). The read byte count (N)
cannot be 0.
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