82NM10 Datasheet, PDF (163/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
1. On detecting the lockup the SECOND_TO_STS bit is set. Chipset sends a message
with the Watchdog (WD) Event status bit set (and any other bits that must also be
set). This message is sent as soon as the lockup is detected, and is sent with the
next (incremented) sequence number.
2. After step 1, Chipset sends a message every heartbeat period until some external
intervention occurs.
3. Rules/steps 4–10 apply if no user intervention (resets, power button presses,
SMBus reset messages) occur after a third timeout of the watchdog timer. If the
intervention occurs before the third timeout, then jump to rule/step 11.
4. After step 3 (third timeout), if the user does a Power Button Override, the system
goes to an S5 state. Chipset continues sending heartbeats at this point.
5. After step 4 (power button override), if the user presses the power button again,
the system should wake to an S0 state and the processor should start executing
the BIOS.
6. If step 5 (power button press) is successful in waking the system, Chipset
continues sending heartbeats until the BIOS clears the SECOND_TO_STS bit. (See
note 2)
7. If step 5 (power button press) is unsuccessful in waking the system, Chipset
continues sending heartbeats. Chipset does not attempt to reboot the system again
until some external intervention occurs (reset, power failure, etc.). (See note 3)
8. After step 3 (third timeout), if a reset is attempted (using a button that pulses
PWROK low or via the message on the SMBus slave I/F), Chipset attempts to reset
the system.
9. If step 8 (reset attempt) is successful, the BIOS is run. Chipset continues sending
heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2)
10. If step 8 (reset attempt), is unsuccessful, Chipset continues sending heartbeats.
Chipset does not attempt to reboot the system again without external intervention.
Note: A system that has locked up and can not be restarted with power button
press is probably broken (bad power supply, short circuit on some bus, etc.)
11. This and the following rules/steps apply if the user intervention (power button
press, reset, SMBus message, etc.) occur prior to the third timeout of the watchdog
timer.
12. After step 1 (second timeout), if the user does a Power Button Override, the system
goes to an S5 state. Chipset continues sending heartbeats at this point.
13. After step 12 (power button override), if the user presses the power button again,
the system should wake to an S0 state and the processor should start executing
the BIOS.
14. If step 13 (power button press) is successful in waking the system, Chipset
continues sending heartbeats until the BIOS clears the SECOND_TO_STS bit. (See
note 2)
15. If step 13 (power button press) is unsuccessful in waking the system, Chipset
continues sending heartbeats. Chipset does not attempt to reboot the system again
until some external intervention occurs (reset, power failure, etc.). (See note 3)
Datasheet
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