82NM10 Datasheet, PDF (182/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Table 5-73.USB Legacy Keyboard State Transitions (Sheet 2 of 2)
Current
State
Action
Data
Value
Next
State
Comment
GateState2 64h / Read
GateState2 60h / Write
GateState2 60h / Read
N/A
XXh
N/A
GateState2 Just stay in same state. Generate an SMI#
if enabled in Bit 2 of Config Register.
PSTATE remains 1.
IDLE
Improper end of sequence. Bit 1 in Config
Register determines if cycle passed through
to 8042 and if SMI# generated. PSTATE
goes to 0. If Bit 7 in Config Register is set,
then SMI# should be generated.
IDLE
Improper end of sequence. Bit 0 in Config
Register determines if cycle passed through
to 8042 and if SMI# generated. PSTATE
goes to 0. If Bit 7 in Config Register is set,
then SMI# should be generated.
5.19
USB EHCI Host Controller (D29:F7)
Chipset contains an Enhanced Host Controller Interface (EHCI) host controller which
supports up to eight USB 2.0 high-speed root ports. USB 2.0 allows data transfers up to
480 Mb/s using the same pins as the eight USB full-speed/low-speed ports. Chipset
contains port-routing logic that determines whether a USB port is controlled by one of
the UHCI controllers or by the EHCI controller. USB 2.0 based Debug Port is also
implemented in Chipset.
A summary of the key architectural differences between the USB UHCI host controllers
and the EHCI host controller are shown in Table 5-74.
Table 5-74.UHCI vs. EHCI
Parameter
Accessible by
Memory Data Structure
Differential Signaling Voltage
Ports per Controller
USB UHCI
I/O space
Single linked list
3.3 V
2
USB EHCI
Memory Space
Separated in to Periodic and Asynchronous
lists
400 mV
8
5.19.1
EHC Initialization
The following descriptions step through the expected Chipset Enhanced Host Controller
(EHC) initialization sequence in chronological order, beginning with a complete power
cycle in which the suspend well and core well have been off.
182
Datasheet