82NM10 Datasheet, PDF (412/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.8.1.7
13.8.1.8
Note:
Bit
Description
0
ACAZ_BREAK_EN — R/W.
0 = Intel HD Audio traffic will not act as a break event.
1 = Intel High Definition Audio traffic acts as a break event, even if the BM_STS-
ZERO_EN and POPUP_EN bits are set. Intel High Definition Audio master activity
will cause BM_STS to be set and will cause a break from C3/C4.
MSC_FUN—Miscellaneous Functionality Register
(PM—D31:F0)
Offset Address: ADh
Default Value: 00h
Power Well:
Resume
Attribute:
Size:
R/W
8-bit
Bit
Description
7:2 Reserved
1:0 USB Transient Disconnect Detect (TDD) — R/W: This field prevents a short Single-
Ended Zero (SE0) condition on the USB ports from being interpreted by the UHCI host
controller as a disconnect. BIOS should set to 11b.
GPIO_ROUT—GPIO Routing Control Register
(PM—D31:F0)
Offset Address: B8h – BBh
Default Value: 00000000h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
32-bit
Resume
Bit
Description
31:30 GPIO15 Route — R/W. See bits 1:0 for description.
Same pattern for GPIO14 through GPIO3
5:4 GPIO2 Route — R/W. See bits 1:0 for description.
3:2 GPIO1 Route — R/W. See bits 1:0 for description.
1:0 GPIO0 Route — R/W. GPIO[15:0] can be routed to cause an SMI or SCI when the
GPIO[n]_STS bit is set. If the GPIO0 is not set to an input, this field has no effect.
If the system is in an S1–S5 state and if the GPE0_EN bit is also set, then the GPIO can
cause a Wake event, even if the GPIO is NOT routed to cause an SMI# or SCI.
00 = No effect.
01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
10 = SCI (if corresponding GPE0_EN bit is also set)
11 = Reserved
GPIOs that are not implemented will not have the corresponding bits implemented in
this register.
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Datasheet