82NM10 Datasheet, PDF (409/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.8.1.4
Bit
Description
1 Power Failure (PWR_FLR) — R/WC. This bit is in the RTC well, and is not cleared by
any type of reset except RTCRST#.
0 = Indicates that the trickle current has not failed since the last time the bit was
cleared. Software clears this bit by writing a 1 to it.
1 = Indicates that the trickle current (from the main battery or trickle supply) was
removed or failed.
NOTE: Clearing CMOS in an ICH-based platform can be done by using a jumper on
RTCRST# or GPI, or using SAFEMODE strap. Implementations should not
attempt to clear CMOS by using a jumper to pull VccRTC low.
0 AFTERG3_EN — R/W. This bit determines what state to go to when power is re-applied
after a power failure (G3 state). This bit is in the RTC well and is not cleared by any
type of reset except writes to CF9h or RTCRST#.
0 = System will return to S0 state (boot) after power is re-applied.
1 = System will return to the S5 state (except if it was in S4, in which case it will return
to S4). In the S5 state, the only enabled wake event is the Power Button or any
enabled wake event that was preserved through the power failure.
NOTE: Bit will be set when THRMTRIP#-based shutdown occurs.
NOTE: RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC
clock period may not be detected by the Chipset.
Cx-STATE_CNF—Cx State Configuration Register
(PM—D31:F0) (Netbook Only)
Offset Address:
Default Value:
Lockable:
Power Well:
A9h
00h
No
Core
Attribute:
Size:
Usage:
R/W
8-bit
ACPI, Legacy
This register is used to enable new C-state related modes.
Bit
Description
7 SCRATCHPAD (SP) — R/W.
6:5 Reserved
4 Popdown Mode Enable (PDME) — R/W. This bit is used in conjunction with the PUME
bit (D31:F0:A9h, bit 3). If PUME is 0, then this bit must also be 0.
0 = The Chipset on Netbook platform will not attempt to automatically return to a
previous C3 or C4 state.
1 = When this bit is a 1 and Chipset on Netbook platform observes that there are no
bus master requests, it can return to a previous C3 or C4 state.
NOTE: This bit is separate from the PUME bit to cover cases where latency issues
permit POPUP but not POPDOWN.
Datasheet
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