82NM10 Datasheet, PDF (649/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
19.1.52 V0CAP — Virtual Channel 0 Resource Capability Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 110h–113h
Default Value: 00000001h
Attribute:
Size:
RO
32 bits
Bit
Description
31:24 Port Arbitration Table Offset (AT) — RO. This VC implements no port arbitration
table since the arbitration is fixed.
23 Reserved.
22:16 Maximum Time Slots (MTS) — RO. This VC implements fixed arbitration; therefore,
this field is not used.
15 Reject Snoop Transactions (RTS) — RO. This VC must be able to take snoopable
transactions.
14 Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not
just advanced packet switching transactions.
13:8 Reserved.
7:0 Port Arbitration Capability (PAC) — RO. This field indicates that this VC uses fixed
port arbitration.
19.1.53 V0CTL — Virtual Channel 0 Resource Control Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 114h–117h
Default Value: 800000FFh
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31 Virtual Channel Enable (EN) — RO. Always set to 1. Virtual Channel 0 cannot be
disabled.
30:27 Reserved.
26:24 Virtual Channel Identifier (VCID) — RO. This field indicates the ID to use for this
virtual channel.
23:20 Reserved.
19:17 Port Arbitration Select (PAS) — R/W. This field indicates which port table is being
programmed. The root complex takes no action on this setting since the arbitration is
fixed and there is no arbitration table.
16 Load Port Arbitration Table (LAT) — RO. The root port does not implement an
arbitration table for this virtual channel.
15:8 Reserved.
Datasheet
649