82NM10 Datasheet, PDF (345/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI-to-PCI Bridge Registers (D30:F0)
12.1.10 SMLT—Secondary Master Latency Timer Register
(PCI-PCI—D30:F0)
Offset Address: 1Bh
Default Value: 00h
Attribute:
Size:
R/W, RO
8 bits
This timer controls the amount of time the Chipset PCI-to-PCI bridge will burst data on
its secondary interface. The counter starts counting down from the assertion of
FRAME#. If the grant is removed, then the expiration of this counter will result in the
de-assertion of FRAME#. If the grant has not been removed, then the Chipset PCI-to-
PCI bridge may continue ownership of the bus.
Bit
Description
7:3 Master Latency Timer Count (MLTC) — R/W. This 5-bit field indicates the number
of PCI clocks, in 8-clock increments, that the Chipset remains as master of the bus.
2:0 Reserved
12.1.11 IOBASE_LIMIT—I/O Base and Limit Register
(PCI-PCI—D30:F0)
Offset Address: 1Ch-1Dh
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:12 I/O Limit Address Limit bits[15:12] — R/W. I/O Base bits corresponding to
address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.
11:8 II/O Limit Address Capability (IOLC) — RO. Indicates that the bridge does not
support 32-bit I/O addressing.
7:4 I/O Base Address (IOBA) — R/W. I/O Base bits corresponding to address lines
15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h.
3:0 I/O Base Address Capability (IOBC) — RO. Indicates that the bridge does not
support 32-bit I/O addressing.
12.1.12 SECSTS—Secondary Status Register (PCI-PCI—D30:F0)
Offset Address: 1Eh–1Fh
Default Value: 0280h
Attribute:
Size:
R/WC, RO
16 bits
Note:
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
Description
15 Detected Parity Error (DPE) — R/WC.
0 = Parity error not detected.
1 = Chipset PCI bridge detected an address or data parity error on the PCI bus
14 Received System Error (RSE) — R/WC.
0 = SERR# assertion not received
1 = SERR# assertion is received on PCI.
Datasheet
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