82NM10 Datasheet, PDF (141/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Table 5-57.Break Events (Netbook)
Event
Breaks
from
Comment
Any unmasked interrupt goes
active
Any internal event that cause an
NMI or SMI#
Any internal event that cause
INIT# to go active
Any bus master request
(internal, external or DMA, or
BM_BUSY#) goes active and
BM_RLD=1 (D31:F0:Offset
PMBASE+04h: bit 1)
Processor Pending Break Event
Indication
C2, C3, C4
C2, C3, C4
IRQ[0:15] when using the 8259s, IRQ[0:23]
for I/O APIC. Since SCI is an interrupt, any SCI
will also be a break event.
Many possible sources
C2, C3, C4
C3, C4
Could be indicated by the keyboard controller
via the RCIN input signal.
Need to wake up processor so it can do snoops
C2, C3, C4
NOTE: If the PUME bit (D31:F0: Offset A9h: bit
3) is set, then bus master activity will
NOT be treated as a break event.
Instead, there will be a return only to
the C2 state.
Only available if FERR# enabled for break event
indication (See FERR# Mux Enable in GCS,
Chipset Config Registers:Offset 3410h:bit 6)
5.14.5.1
Transition Rules among S0/Cx and Throttling States
The following priority rules and assumptions apply among the various S0/Cx and
throttling states:
• Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This
is because the processor can only perform one register access at a time and Sleep
states have higher priority than thermal throttling.
• When the SLP_EN bit is set (system going to a S1–S5 sleep state), the THTL_EN
and FORCE_THTL bits can be internally treated as being disabled (no throttling
while going to sleep state).
• (Netbook) If the THTL_EN or FORCE_THTL bits are set, and a Level 2, Level 3, or
Level 4 read then occurs, the system should immediately go and stay in a C2, C3,
or C4 state until a break event occurs. A Level 2, Level 3, or Level 4 read has
higher priority than the software initiated throttling.
• (Netbook) After an exit from a C2, C3, or C4 state (due to a Break event), and if
the THTL_EN or FORCE_THTL bits are still set the system will continue to throttle
STPCLK#. Depending on the time of break event, the first transition on STPCLK#
active can be delayed by up to one THRM period (1024 PCI clocks = 30.72 µs).
• The Host controller must post Stop-Grant cycles in such a way that the processor
gets an indication of the end of the special cycle prior to Chipset observing the
Stop-Grant cycle. This ensures that the STPCLK# signals stays active for a
sufficient period after the processor observes the response phase.
Datasheet
141