82NM10 Datasheet, PDF (392/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
4 IRQ12 ECL — R/W.
0 = Edge
1 = Level
3 IRQ11 ECL — R/W.
0 = Edge
1 = Level
2 IRQ10 ECL — R/W.
0 = Edge
1 = Level
1 IRQ9 ECL — R/W.
0 = Edge
1 = Level
0 Reserved. Must be 0.
Description
13.5
Advanced Programmable Interrupt Controller
(APIC)(D31:F0)
13.5.1
APIC Register Map (LPC I/F—D31:F0)
The APIC is accessed via an indirect addressing scheme. Two registers are visible by
software for manipulation of most of the APIC registers. These registers are mapped
into memory space. The registers are shown in Table 13-122.
Table 13-122.APIC Direct Registers (LPC I/F—D31:F0)
Address
Mnemoni
c
Register Name
FEC0_0000h
FEC0_0010h
FECO_0040h
IND
DAT
EOIR
Index
Data
EOI
Size
8 bits
32 bits
32 bits
Type
R/W
R/W
WO
Table 13-123 lists the registers which can be accessed within the APIC via the Index
Register. When accessing these registers, accesses must be done one DWord at a time.
For example, software should not access byte 2 from the Data register before accessing
bytes 0 and 1. The hardware will not attempt to recover from a bad programming
model in this case.
Table 13-123.APIC Indirect Registers (LPC I/F—D31:F0)
Index
Mnemonic
Register Name
00
01
02–0F
10–11
ID
VER
—
REDIR_TBL0
Identification
Version
Reserved
Redirection Table 0
Size
32 bits
32 bits
—
64 bits
Type
R/W
RO
RO
R/W, RO
392
Datasheet