82NM10 Datasheet, PDF (336/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
11.3.21 PMSK1—Polling Mask 1 Register
(ASF Controller—B1:D8:F0)
Offset Address: F8h
Default Value: XXh
Attribute:
Size:
R/W
8 bits
This register provides software an interface for the Polling #1 Data Mask.
Bit
Description
7:0 Polling Mask for Polling Descriptor #1 (POL1_MSK) — R/W. This field is used to
read and write the data mask for Polling Descriptor #1. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
11.3.22 PMSK2—Polling Mask 2 Register
(ASF Controller—B1:D8:F0)
Offset Address: F9h
Default Value: XXh
Attribute:
Size:
R/W
8 bits
This register provides software an interface for the Polling #2 Data Mask.
Bit
Description
7:0 Polling Mask for Polling Descriptor #2 (POL2_MSK) — R/W. This field is used to
read and write the data mask for Polling Descriptor #2. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
11.3.23 PMSK3—Polling Mask 3 Register
(ASF Controller—B1:D8:F0)
Offset Address: FAh
Default Value: XXh
Attribute:
Size:
R/W
8 bits
This register provides software an interface for the Polling #3 Data Mask.
Bit
Description
7:0 Polling Mask for Polling Descriptor #3 (POL3_MSK) — R/W. This register is used
to read and write the data mask for Polling Descriptor #3. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
11.3.24 PMSK4—Polling Mask 4 Register
(ASF Controller—B1:D8:F0)
Offset Address: FBh
Default Value: XXh
Attribute:
Size:
R/W
8 bits
This register provides software an interface for the Polling #4 Data Mask.
Bit
Description
7:0 Polling Mask for Polling Descriptor #4 (POL4_MSK) — R/W. This register is used
to read and write the data mask for Polling Descriptor #4. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
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Datasheet