82NM10 Datasheet, PDF (429/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
17
16:15
14
13
12
11
10:8
7
6
5
4
Description
LEGACY_USB2_EN — R/W.
0 = Disable
1 = Enables legacy USB2 logic to cause SMI#.
Reserved
PERIODIC_EN — R/W.
0 = Disable.
1 = Enables the Chipset to generate an SMI# when the PERIODIC_STS bit
(PMBASE + 34h, bit 14) is set in the SMI_STS register (PMBASE + 34h).
TCO_EN — R/W.
0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is
set, SMIs that are caused by re-routed NMIs will not be gated by the TCO_EN
bit. Even if the TCO_EN bit is 0, NMIs will still be routed to cause SMIs.
1 = Enables the TCO logic to generate SMI#.
NOTE: This bit cannot be written once the TCO_LOCK bit is set.
Reserved
MCSMI_ENMicrocontroller SMI Enable (MCSMI_EN) — R/W.
0 = Disable.
1 = Enables Chipset to trap accesses to the microcontroller range (62h or 66h)
and generate an SMI#. Note that “trapped’ cycles will be claimed by the
Chipset on PCI, but not forwarded to LPC.
Reserved
BIOS Release (BIOS_RLS) — WO.
0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect.
1 = Enables the generation of an SCI interrupt for ACPI software when a one is
written to this bit position by BIOS software.
NOTE: GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set.
Software must take great care not to set the BIOS_RLS bit (which causes
GBL_STS to be set) if the SCI handler is not in place.
Software SMI# Timer Enable (SWSMI_TMR_EN) — R/W.
0 = Disable. Clearing the SWSMI_TMR_EN bit before the timer expires will reset
the timer and the SMI# will not be generated.
1 = Starts Software SMI# Timer. When the SWSMI timer expires (the timeout
period depends upon the SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is
set and an SMI# is generated. SWSMI_TMR_EN stays set until cleared by
software.
APMC_EN — R/W.
0 = Disable. Writes to the APM_CNT register will not cause an SMI#.
1 = Enables writes to the APM_CNT register to cause an SMI#.
SLP_SMI_EN — R/W.
0 = Disables the generation of SMI# on SLP_EN. Note that this bit must be 0
before the software attempts to transition the system into a sleep state by
writing a 1 to the SLP_EN bit.
1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT register) will generate an
SMI#, and the system will not transition to the sleep state based on that
write to the SLP_EN bit.
Datasheet
429