82NM10 Datasheet, PDF (627/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
19.1.11 HEADTYP—Header Type Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 0Eh
Default Value: 81h
Attribute:
Size:
RO
8 bits
Bit
Description
7 Multi-Function Device — RO.
0 = Single-function device.
1 = Multi-function device.
6:0 Configuration Layout. Hardwired to 01h, which indicates a PCI-to-PCI bridge.
19.1.12 BNUM—Bus Number Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 18–1Ah
Default Value: 000000h
Attribute:
Size:
R/W
24 bits
Bit
Description
23:16 Subordinate Bus Number (SBBN) — R/W. This field indicates the highest PCI bus
number below the bridge.
15:8 Secondary Bus Number (SCBN) — R/W. This field indicates the bus number the
port.
7:0 Primary Bus Number (PBN) — R/W. This field indicates the bus number of the
backbone.
19.1.13 IOBL—I/O Base and Limit Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 1Ch–1Dh
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:12 I/O Limit Address (IOLA) — R/W. This field contains the I/O Base bits
corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be
padded to FFFh.
11:8 I/O Limit Address Capability (IOLC) — R/O. This field indicates that the bridge does not
support 32-bit I/O addressing.
7:4 I/O Base Address (IOBA) — R/W. This field contains the I/O Base bits
corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be
padded to 000h.
3:0 I/O Base Address Capability (IOBC) — R/O. This field indicates that the bridge
does not support 32-bit I/O addressing.
Datasheet
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