82NM10 Datasheet, PDF (654/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
19.1.59 CEM — Correctable Error Mask Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 154h–157h
Default Value: 00000000h
Attribute:
Size:
R/WO
32 bits
When set, the corresponding error in the CES register is masked, and the logged error
will cause no action. When cleared, the corresponding error is enabled.
Bit
Description
31:13 Reserved
12
11:9
8
Replay Timer Timeout Mask (RTT) — R/WO.
0 = No mask
1 = Mask for replay timer timeout.
Reserved
Replay Number Rollover Mask (RNR) — R/WO.
0 = No mask
1 = Mask for replay number rollover.
7 Bad DLLP Mask (BD) — R/WO.
0 = No mask
1 = Mask for bad DLLP reception.
6 Bad TLP Mask (BT) — R/WO.
0 = No mask
1 = Mask for bad TLP reception.
5:1 Reserved
0 Receiver Error Mask (RE) — R/WO.
0 = No mask
1 = Mask for receiver errors.
19.1.60 AECC — Advanced Error Capabilities and Control Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 158h–15Bh
Default Value: 00000000h
Attribute:
Size:
RO
32 bits
Bit
Description
31:9
8
7
6
5
4:0
Reserved
ECRC Check Enable (ECE) — RO. ECRC is not supported.
ECRC Check Capable (ECC) — RO. ECRC is not supported.
ECRC Generation Enable (EGE) — RO. ECRC is not supported.
ECRC Generation Capable (EGC) — RO. ECRC is not supported.
First Error Pointer (FEP) — RO.
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Datasheet