82NM10 Datasheet, PDF (361/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.1.14 ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0)
Offset Address: 44h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/W
8 bit
ACPI, Legacy
Core
Bit
Description
7 ACPI Enable (ACPI_EN) — R/W.
0 = Disable.
1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the
ACPI power management function is enabled. Note that the APM power
management ranges (B2/B3h) are always enabled and are not affected by this bit.
6:3 Reserved
2:0 SCI IRQ Select (SCI_IRQ_SEL) — R/W.
Specifies on which IRQ the SCI will internally appear. If not using the APIC, the SCI
must be routed to IRQ9–11, and that interrupt is not sharable with the SERIRQ stream,
but is shareable with other PCI interrupts. If using the APIC, the SCI can also be
mapped to IRQ20–23, and can be shared with other interrupts.
Bits
000b
001b
010b
011b
100b
101b
110b
111b
SCI Map
IRQ9
IRQ10
IRQ11
Reserved
IRQ20 (Only available if APIC enabled)
IRQ21 (Only available if APIC enabled)
IRQ22 (Only available if APIC enabled)
IRQ23 (Only available if APIC enabled)
NOTE: When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be
programmed for active-high reception. When the interrupt is mapped to APIC
interrupts 20 through 23, the APIC should be programmed for active-low
13.1.15 GPIOBASE—GPIO Base Address Register (LPC I/F —
D31:F0)
Offset Address: 48h–4Bh
Default Value: 00000001h
Attribute:
Size:
R/W, RO
32 bit
Bit
Description
31:16 Reserved. Always 0.
15:6 Base Address (BA) — R/W. Provides the 64 bytes of I/O space for GPIO.
5:1 Reserved. Always 0.
0 RO. Hardwired to 1 to indicate I/O space.
Datasheet
361