82NM10 Datasheet, PDF (41/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Introduction
Enhanced Power Management
Intel NM10 Express Chipset’s power management functions include enhanced clock
control and various low-power (suspend) states (e.g., Suspend-to-RAM and Suspend-
to-Disk). A hardware-based thermal management circuit permits software-independent
entrance to low-power states. This chipset contains full support for the Advanced
Configuration and Power Interface (ACPI) Specification, Revision 3.0.
Manageability
Intel NM10 Express Chipset integrates several functions designed to manage the
system and lower the total cost of ownership (TCO) of the system. These system
management functions are designed to report errors, diagnose the system, and recover
from system lockups without the aid of an external microcontroller.
• TCO Timer. Chipset’s integrated programmable TCO timer is used to detect
system locks. The first expiration of the timer generates an SMI# that the system
can use to recover from a software lock. The second expiration of the timer causes
a system reset to recover from a hardware lock.
• Processor Present Indicator. Chipset looks for the processor to fetch the first
instruction after reset. If the processor does not fetch the first instruction, Chipset
will reboot the system.
• ECC Error Reporting. When detecting an ECC error, the host controller has the
ability to send one of several messages to Chipset. The host controller can instruct
Chipset to generate either an SMI#, NMI, SERR#, or TCO interrupt.
• Function Disable. Chipset provides the ability to disable the following integrated
functions: LAN, USB, LPC, Intel HD Audio, SATA, or SMBus. Once disabled, these
functions no longer decode I/O, memory, or PCI configuration space. Also, no
interrupts or power management events are generated from the disable functions.
• Intruder Detect. Chipset provides an input signal (INTRUDER#) that can be
attached to a switch that is activated by the system case being opened. Chipset can
be programmed to generate an SMI# or TCO interrupt due to an active INTRUDER#
signal.
System Management Bus (SMBus 2.0)
This chipset contains an SMBus Host interface that allows the processor to
communicate with SMBus slaves. This interface is compatible with most I²C devices.
Special I²C commands are implemented.
This chipset's SMBus host controller provides a mechanism for the processor to initiate
communications with SMBus peripherals (slaves). Also, this chipset supports slave
functionality, including the Host Notify protocol. Hence, the host controller supports
eight command protocols of the SMBus interface (see System Management Bus
(SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write
Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.
Datasheet
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