82NM10 Datasheet, PDF (365/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
Description
2:0 COMA Decode Range — R/W. This field determines which range to decode for the
COMA Port.
000 = 3F8h – 3FFh (COM1)
001 = 2F8h – 2FFh (COM2)
010 = 220h – 227h
011 = 228h – 22Fh
100 = 238h – 23Fh
101 = 2E8h – 2EFh (COM4)
110 = 338h – 33Fh
111 = 3E8h – 3EFh (COM3)
13.1.21 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)
Offset Address: 82h – 83h
Default Value: 0000h
Attribute:
Size:
Power Well:
R/W
16 bit
Core
Bit
Description
15:14 Reserved
13 CNF2_LPC_EN — R/W. Microcontroller Enable # 2.
0 = Disable.
1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This
range is used for a microcontroller.
12 CNF1_LPC_EN — R/W. Super I/O Enable.
0 = Disable.
1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This
range is used for Super I/O devices.
11 MC_LPC_EN — R/W. Microcontroller Enable # 1.
0 = Disable.
1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This
range is used for a microcontroller.
10 KBC_LPC_EN — R/W. Keyboard Enable.
0 = Disable.
1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This
range is used for a microcontroller.
9 GAMEH_LPC_EN — R/W. High Gameport Enable
0 = Disable.
1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This
range is used for a gameport.
8 GAMEL_LPC_EN — R/W. Low Gameport Enable
0 = Disable.
1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This
range is used for a gameport.
7:4 Reserved
Datasheet
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