82NM10 Datasheet, PDF (537/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

EHCI Controller Registers (D29:F7)
16.2.2.1
• D3-to-D0 reset
The second set at offsets MEM_BASE + 60h to the end of the implemented register
space are implemented in the Suspend power well. Unless otherwise noted, the
suspend well registers are reset by the assertion of either of the following:
• Suspend well hardware reset
• HCRESET
USB2.0_CMD—USB 2.0 Command Register
Offset:
MEM_BASE + 20–23h
Default Value: 00080000h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:24 Reserved. These bits are reserved and should be set to 0 when writing this register.
23:16
Interrupt Threshold Control — R/W. System software uses this field to select the
maximum rate at which the host controller will issue interrupts. The only valid values
are defined below. If software writes an invalid value to this register, the results are
undefined.
Value
00h
01h
02h
04h
08h
10h
20h
40h
Maximum Interrupt Interval
Reserved
1 micro-frame
2 micro-frames
4 micro-frames
8 micro-frames (default, equates to 1 ms)
16 micro-frames (2 ms)
32 micro-frames (4 ms)
64 micro-frames (8 ms)
15:8
11:8
7
6
Reserved. These bits are reserved and should be set to 0 when writing this register.
Unimplemented Asynchronous Park Mode Bits. Hardwired to 000b indicating the host
controller does not support this optional feature.
Light Host Controller Reset — RO. Hardwired to 0. The Chipset does not implement
this optional reset.
Interrupt on Async Advance Doorbell — R/W. This bit is used as a doorbell by
software to tell the host controller to issue an interrupt the next time it advances
asynchronous schedule.
0 = The host controller sets this bit to a 0 after it has set the Interrupt on Async
Advance status bit (D29:F7:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register
to a 1.
1 = Software must write a 1 to this bit to ring the doorbell. When the host controller
has evicted all appropriate cached schedule state, it sets the Interrupt on Async
Advance status bit in the USB2.0_STS register. If the Interrupt on Async Advance
Enable bit in the USB2.0_INTR register (D29:F7:CAPLENGTH + 28h, bit 5) is a 1
then the host controller will assert an interrupt at the next interrupt threshold. See
the EHCI specification for operational details.
NOTE: Software should not write a 1 to this bit when the asynchronous schedule is
inactive. Doing so will yield undefined results.
Datasheet
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