82NM10 Datasheet, PDF (415/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Table 13-129.ACPI and Legacy I/O Register Map (Sheet 2 of 2)
PMBASE
+ Offset
Mnemonic
Register Name
ACPI Pointer
Default
Type
50h
—
Reserved (Nettop Only)
50h
SS_CNT
Intel SpeedStep^® Technology
Control (Netbook Only)
51h–5Fh
—
Reserved
—
54h–57h
C3_RES
C3-Residency Register
—
(Netbook Only)
60h–7Fh
—
Reserved for TCO
—
01h
R/W (special)
—
00000000h
—
RO, R/W
—
—
13.8.3.1
PM1_STS—Power Management 1 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 00h
(ACPI PM1a_EVT_BLK)
0000h
No
Bits 0–7: Core,
Bits 8–15: Resume,
except Bit 11 in RTC
Attribute:
Size:
Usage:
R/WC
16-bit
ACPI or Legacy
If bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the PM1_EN
register, then the Chipset will generate a Wake Event. Once back in an S0 state (or if
already in an S0 state when the event occurs), the Chipset will also generate an SCI if
the SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set.
Note:
Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but
can cause an SMI# or SCI.
Bit
Description
15
Wake Status (WAK_STS) — R/WC. This bit is not affected by hard resets caused
by a CF9 write, but is reset by RSMRST#.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the system is in one of the sleep states (via the SLP_EN
bit) and an enabled wake event occurs. Upon setting this bit, the Chipset will
transition the system to the ON state.
If the AFTERG3_EN bit is not set and a power failure (such as removed batteries on
a Netbook platform) occurs without the SLP_EN bit set, the system will return to an
S0 state when power returns, and the WAK_STS bit will not be set.
If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit
having been set, the system will go into an S5 state when power returns, and a
subsequent wake event will cause the WAK_STS bit to be set. Note that any
subsequent wake event would have to be caused by either a Power Button press, or
an enabled wake event that was preserved through the power failure (enable bit in
the RTC well).
Datasheet
415