82NM10 Datasheet, PDF (211/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.22
Note:
5.22.1
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a potentially
lower-cost alternative for system flash versus the Firmware Hub on the LPC bus.
The 4-pin SPI interface consists of clock (CLK), master data out (Master Out Slave In
(MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select
(CS#).
Communication on the SPI bus is done with a Master – Slave protocol. The typical bus
topology consists of a single SPI Master with a single SPI Slave (flash device). The
Slave is connected to Chipset and is implemented as a tri-state bus.
When SPI is selected by the Boot BIOS Destination Strap and a SPI device is detected
by Chipset, LPC based BIOS flash is disabled.
Flash Device Configurations
Chipset SPI flash may be used in two configurations. Table 5-85 focuses on these
various configurations involving Chipset.
Table 5-85.SPI Implementation Options
Configuration
1
2
System
BIOS
Location
FWH
SPI
System BIOS
and Intel
AMT Shared
Flash
No
No
FWH
Present
Yes
No
Number of
SPI
Device(s)
0
1
Note:
Chipset SPI interface supports a single Chip Select pin for a single SPI device.
5.22.2
5.22.2.1
SPI Device Compatibility Requirements
A variety of SPI flash devices exist in the market. In order for a SPI device to be
compatible with Chipset it must meet the minimum requirements detailed in the
following sections.
Chipset SPI Based BIOS Only Configuration Requirements
A SPI flash device must meet the following minimum requirements to be compatible
with Chipset in a non-shared flash configuration:
• Erase size capability of at least one of the following: 64 KB, 32 KB, 4 KB, 2 KB, 512
bytes, or 256 bytes.
• Required command set and associated opcodes (Refer to Section 5.22.3.1).
• Device identification command (Refer to Section 5.22.3.2).
• Device must support multiple writes to a page without requiring a preceding erase
cycle (Refer to Section 5.22.4)
Datasheet
211