82NM10 Datasheet, PDF (444/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.10
General Purpose I/O Registers (D31:F0)
The control for the general purpose I/O signals is handled through a separate 64-byte
I/O space. The base offset for this space is selected by the GPIOBASE register.
GPIO Register I/O Address Map
Table 13-131.Registers to Control GPIO Address Map
GPIOBASE
+ Offset
Mnemonic
Register Name
General Registers
00h–03h
04h–07h
08h–0Bh
0Ch–0Fh
10h–13h
GPIO_USE_SEL
GP_IO_SEL
—
GP_LVL
GPIO Use Select
GPIO Input/Output Select
Reserved
GPIO Level for Input or Output
Reserved
14h–17h
18h–1Bh
1Ch–1Fh
20–2Bh
2C–2Fh
30h–33h
34h–37h
38h–3Bh
Output Control Registers
—
GPO_BLINK
Reserved
GPIO Blink Enable
—
Reserved
Input Control Registers
—
GPI_INV
GPIO_USE_SEL2
Reserved
GPIO Signal Invert
GPIO Use Select 2 [63:32]
GP_IO_SEL2
GP_LVL2
GPIO Input/Output Select 2
[63:32]
GPIO Level for Input or Output 2
[63:32]
Default
Access
1F2AF7FFh
E0E8FFFFh
—
02FE0000h
—
R/W
R/W
—
R/W
—
—
00040000h
—
—
R/W
—
—
00000000h
000300FEh
000000F0h
00030003h
—
R/W
R/W
R/W
R/W
444
Datasheet