82NM10 Datasheet, PDF (167/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Table 5-70.SATA Feature Description
Staggered Spin-Up
Enables the host the ability to spin up hard drives
sequentially to prevent power load problems on boot
Command Completion
Coalescing
Reduces interrupt and completion overhead by allowing a
specified number of commands to complete and then
generating an interrupt to process the commands
Port Multiplier
A mechanism for one active host connection to
communicate with multiple devices
External SATA
Technology that allows for an outside the box connection of
up to 2 meters (when using the cable defined in SATA-IO)
5.16.1
5.16.1.1
Note:
5.16.1.2
Theory of Operation
Standard ATA Emulation
Chipset contains a set of registers that shadow the contents of the legacy IDE registers.
The behavior of the Command and Control Block registers, PIO, and DMA data
transfers, resets, and interrupts are all emulated.
Chipset will assert INTR when the master device completes the EDD command
regardless of the command completion status of the slave device. If the master
completes EDD first, an INTR is generated and BSY will remain '1' until the slave
completes the command. If the slave completes EDD first, BSY will be '0' when the
master completes the EDD command and asserts INTR. Software must wait for busy to
clear (0) before completing an EDD command, as required by the ATA5 through ATA7
(T13) industry standards.
48-Bit LBA Operation
The SATA host controller supports 48-bit LBA through the host-to-device register FIS
when accesses are performed via writes to the task file. The SATA host controller will
ensure that the correct data is put into the correct byte of the host-to-device FIS.
There are special considerations when reading from the task file to support 48-bit LBA
operation. Software may need to read all 16-bits. Since the registers are only 8-bits
wide and act as a FIFO, a bit must be set in the device/control register, which is at
offset 3F6h for primary and 376h for secondary (or their native counterparts).
If software clears bit 7 of the control register before performing a read, the last item
written will be returned from the FIFO. If software sets bit 7 of the control register
before performing a read, the first item written will be returned from the FIFO.
Datasheet
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