82NM10 Datasheet, PDF (606/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
18.2.17 CORBUBASE—CORB Upper Base Address Register
(Intel HD Audio Controller—D27:F0)
Memory Address:HDBAR + 44h
Attribute:
R/W
Default Value:
00000000hSize:32 bits
Bit
Description
31:0
CORB Upper Base Address — R/W. This field is the upper 32 bits of the address of
the Command Output Ring buffer. This register field must not be written when the DMA
engine is running or the DMA transfer may be corrupted.
18.2.18 CORBWP—CORB Write Pointer Register
(Intel HD Audio Controller—D27:F0)
Memory Address:HDBAR + 48h
Attribute:
R/W
Default Value:
0000hSize:16 bits
Bit
Description
15:8
7:0
Reserved.
CORB Write Pointer — R/W. Software writes the last valid CORB entry offset into this
field in DWord granularity. The DMA engine fetches commands from the CORB until the
Read pointer matches the Write pointer. Supports 256 CORB entries (256x4B = 1KB).
This register field may be written when the DMA engine is running.
18.2.19 CORBRP—CORB Read Pointer Register
(Intel HD Audio Controller—D27:F0)
Memory Address:HDBAR + 4Ah
Attribute:
R/W
Default Value:
0000hSize:16 bits
Bit
Description
15
14:8
7:0
CORB Read Pointer Reset — R/W. Software writes a 1 to this bit to reset the CORB
Read Pointer to 0 and clear any residual prefetched commands in the CORB hardware
buffer within the Intel HD Audio controller. The hardware will physically update this bit
to 1 when the CORB Pointer reset is complete. Software must read a 1 to verify that the
reset completed correctly. Software must clear this bit back to 0 and read back the 0 to
verify that the clear completed correctly. The CORB DMA engine must be stopped prior
to resetting the Read Pointer or else DMA transfer may be corrupted.
Reserved.
CORB Read Pointer (CORBRP) — RO. Software reads this field to determine how
many commands it can write to the CORB without over-running. The value read
indicates the CORB Read Pointer offset in DWord granularity. The offset entry read from
this field has been successfully fetched by the DMA controller and may be over-written
by software. Supports 256 CORB entries (256 x 4B=1KB). This field may be read while
the DMA engine is running.
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