82NM10 Datasheet, PDF (210/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Table 5-84.Host Notify Format (Sheet 2 of 2)
Bit
Description
19 ACK
27:20 Data Byte Low — 8 bits
28 ACK
36:29 Data Byte High — 8 bits
37 ACK
38 Stop
Driven By
Chipset
External
Master
Chipset
External
Master
Chipset
External
Master
Comment
Loaded into the Notify Data Low Byte
Register
Loaded into the Notify Data High Byte
Register
5.21
Intel HD Audio Overview
chipset’s controller communicates with the external codec(s) over the Intel High
Definition Audio serial link. The controller consists of a set of DMA engines that are
used to move samples of digitally encoded data between system memory and an
external codec(s). Chipset implements four output DMA engines and 4 input DMA
engines. The output DMA engines move digital data from system memory to a D-A
converter in a codec. Chipset implements a single Serial Data Output signal
(HDA_SDOUT) that is connected to all external codecs. The input DMA engines move
digital data from the A-D converter in the codec to system memory. Chipset
implements three Serial Digital Input signals (HDA_SDI[2:0]) supporting up to three
codecs.
Audio software renders outbound and processes inbound data to/from buffers in
system memory. The location of individual buffers is described by a Buffer Descriptor
List (BDL) that is fetched and processed by the controller. The data in the buffers is
arranged in a predefined format. The output DMA engines fetch the digital data from
memory and reformat it based on the programmed sample rate, bit/sample and
number of channels. The data from the output DMA engines is then combined and
serially sent to the external codecs over the Intel High Definition Audio link. The input
DMA engines receive data from the codecs over the Intel High Definition Audio link and
format the data based on the programmable attributes for that stream. The data is
then written to memory in the predefined format for software to process. Each DMA
engine moves one stream of data. A single codec can accept or generate multiple
streams of data, one for each A-D or D-A converter in the codec. Multiple codecs can
accept the same output stream processed by a single DMA engine.
Codec commands and responses are also transported to and from the codecs via DMA
engines.
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Datasheet