82NM10 Datasheet, PDF (145/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Table 5-58.Sleep Types
Sleep
Type
S1
S3
S4
S5
Comment
Chipset asserts the STPCLK# signal. It also has the option to assert CPUSLP#
signal (only supported on Nettop platforms). This lowers the processor’s power
consumption. No snooping is possible in this state.
Chipset asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical
circuits. Power is only retained to devices needed to wake from this sleeping state,
as well as to the memory.
Chipset asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power to
the memory subsystem. Only devices needed to wake from this state should be
powered.
Same power state as S4. Chipset asserts SLP_S3#, SLP_S4# and SLP_S5#.
5.14.7.3 Exiting Sleep States
Sleep states (S1–S5) are exited based on Wake events. The Wake events forces the
system to a full on state (S0), although some non-critical subsystems might still be
shut off and have to be brought back manually. For example, the hard disk may be shut
off during a sleep state, and have to be enabled via a GPIO pin before it can be used.
Upon exit from Chipset-controlled Sleep states, the WAK_STS bit is set. The possible
causes of Wake Events (and their restrictions) are shown in Table 5-59.
Note:
(Netbook Only) If the BATLOW# signal is asserted, Chipset does not attempt to wake
from an S1–S5 state, even if the power button is pressed. This prevents the system
from waking when the battery power is insufficient to wake the system. Wake events
that occur while BATLOW# is asserted are latched by Chipset, and the system wakes
after BATLOW# is de-asserted.
Table 5-59.Causes of Wake Events
Cause
RTC Alarm
Power Button
GPI[0:15]
States Can
Wake From¹
How Enabled
S1–S5² Set RTC_EN bit in PM1_EN register
S1–S5
S1–S5²
Always enabled as Wake event
GPE0_EN register
Classic USB
LAN
RI#
Intel HD Audio
Primary PME#
Secondary PME#
S1–S5
S1–S5
S1–S5²
S1–S5²
S1–S5
S1–S5
NOTE: GPIs that are in the core well are not capable of waking
the system from sleep states where the core well is not
powered.
Set USB1_EN, USB 2_EN, USB3_EN, and USB4_EN bits in
GPE0_EN register
Will use PME#. Wake enable set with LAN logic.
Set RI_EN bit in GPE0_EN register
Set AC97_EN bit in GPE0_EN register
PME_B0_EN bit in GPE0_EN register
Set PME_EN bit in GPE0_EN register.
Datasheet
145