82NM10 Datasheet, PDF (140/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.14.4.1
5.14.4.2
PCI Express* SCI
PCI Express ports and the CPU (via DMI) have the ability to cause PME using messages.
When a PME message is received, Chipset will set the PCI_EXP_STS bit. If the
PCI_EXP_EN bit is also set, Chipset can cause an SCI via the GPE1_STS register.
PCI Express* Hot-Plug
PCI Express has a Hot-Plug mechanism and is capable of generating a SCI via the GPE1
register. It is also capable of generating an SMI. However, it is not capable of
generating a wake event.
5.14.5
Dynamic Processor Clock Control
Chipset has extensive control for dynamically starting and stopping system clocks. The
clock control is used for transitions among the various S0/Cx states, and processor
throttling. Each dynamic clock control method is described in this section. The various
sleep states may also perform types of non-dynamic clock control.
Chipset supports the ACPI C0 and C1 states (in Nettop) or C0, C1, C2, C3 and C4 (in
Netbook) states.
The Dynamic Processor Clock control is handled using the following signals:
• STPCLK#: Used to halt processor instruction stream.
• (Netbook) STP_CPU#: Used to stop processor’s clock
• (Netbook) DPSLP#: Used to force Deeper Sleep for processor.
• (Netbook) DPRSLPVR: Used to lower voltage of VRM during C4 state.
• (Netbook) DPRSTP#: Used to lower voltage of VRM during C4 state
The C1 state is entered based on the processor performing an auto halt instruction.
(Netbook) The C2 state is entered based on the processor reading the Level 2 register
in Chipset. It can also be entered from C3 or C4 states if bus masters require snoops
and the PUME bit (D31:F0: Offset A9h: bit 3) is set.
(Netbook) The C3 state is entered based on the processor reading the Level 3 register
in Chipset and when the C4 on C3_EN bit is clear (D31:F0:Offset A0:bit 7). This state
can also be entered after a temporary return to C2 from a prior C3 or C4 state.
(Netbook) The C4 state is entered based on the processor reading the Level 4 register
in Chipset, or by reading the Level 3 register when the C4onC3_EN bit is set. This state
can also be entered after a temporary return to C2 from a prior C4 state.
A C1 state in Nettop Only or a C1, C2, C3, or C4 state in Netbook Only ends due to a
Break event. Based on the break event, Chipset returns the system to C0 state.
(Netbook) Table 5-57 lists the possible break events from C2, C3, or C4. The break
events from C1 are indicated in the processor’s datasheet.
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Datasheet