82NM10 Datasheet, PDF (136/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Table 5-54.State Transition Rules for Chipset (Sheet 2 of 2)
Present
State
G0/S0/C2
(Netbook
Only)
G0/S0/C3
(Netbook
Only)
Transition Trigger
• Any Enabled Break Event
• Power Button Override
• Power Failure
• Previously in C3/C4 and bus
masters idle
• Any Enabled Break Event
• Any Bus Master Event
• Power Button Override
• Power Failure
• Previously in C4 and bus masters
idle
G0/S0/C4
(Netbook
Only)
• Any Enabled Break Event
• Any Bus Master Event
• Power Button Override
• Power Failure
G1/S1,
G1/S3, or
G1/S4
G2/S5
G3
• Any Enabled Wake Event
• Power Button Override
• Power Failure
• Any Enabled Wake Event
• Power Failure
• Power Returns
Next State
• G0/S0/C0
• G2/S5
• G3
• C3 or C4 - depending on PDME bit
(D31:F0: Offset A9h: bit 4)
• G0/S0/C0
• G0/S0/C2 - if PUME bit (D31:F0: Offset
A9h: bit 3) is set, else G0/S0/C0
• G2/S5
• G3
• C4 - depending on PDME bit (D31:F0:
Offset A9h: bit 4
• G0/S0/C0
• G0/S0/C2 - if PUME bit (D31:F0: Offset
A9h: bit 3) is set, else G0/S0/C0
• G2/S5
• G3
• G0/S0/C0 (See Note 2)
• G2/S5
• G3
• G0/S0/C0 (See Note 2)
• G3
• Optional to go to S0/C0 (reboot) or
G2/S5 (stay off until power button
pressed or other wake event). (See
Note 1 and 2)
NOTES:
1.
Some wake events can be preserved through power failure.
2.
Transitions from the S1–S5 or G3 states to the S0 state are deferred until BATLOW# is
inactive in Netbook configurations.
5.14.3
System Power Planes
The system has several independent power planes, as described in Table 5-55. Note
that when a particular power plane is shut off, it should go to a 0 V level.
136
Datasheet