82NM10 Datasheet, PDF (404/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.7.5
RST_CNT—Reset Control Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
CF9h
00h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:4 Reserved
3 Full Reset (FULL_RST) — R/W. This bit is used to determine the states of SLP_S3#,
SLP_S4#, and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1),
after PWROK going low (with RSMRST# high), or after two TCO timeouts.
0 = Chipset will keep SLP_S3#, SLP_S4# and SLP_S5# high.
1 = Chipset will drive SLP_S3#, SLP_S4# and SLP_S5# low for 3 – 5 seconds.
NOTE: When this bit is set, it also causes the full power cycle (SLP_S3/4/5# assertion)
in response to SYS_RESET#, PWROK#, and Watchdog timer reset sources.
2 Reset CPU (RST_CPU) — R/W. When this bit transitions from a 0 to a 1, it initiates a
hard or soft reset, as determined by the SYS_RST bit (bit 1 of this register).
1 System Reset (SYS_RST) — R/W. This bit is used to determine a hard or soft reset to
the processor.
0 = When RST_CPU bit goes from 0 to 1, the Chipset performs a soft reset by
activating INIT# for 16 PCI clocks.
1 = When RST_CPU bit goes from 0 to 1, the Chipset performs a hard reset by
activating PLTRST# and SUS_STAT# active for about 5-6 milliseconds, however
the SLP_S3#, SLP_S4# and SLP_S5# will NOT go active. The Chipset main power
well is reset when this bit is 1. It also resets the resume well bits (except for those
noted throughout the datasheet).
0 Reserved
13.8
Power Management Registers (PM—D31:F0)
The power management registers are distributed within the PCI Device 31: Function 0
space, as well as a separate I/O range. Each register is described below. Unless
otherwise indicate, bits are in the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to
a reserved bit, the value should always be 0. Software should not attempt to use the
value read from a reserved bit, as it may not be consistently 1 or 0.
13.8.1
Power Management PCI Configuration Registers
(PM—D31:F0)
Table 13-127 shows a small part of the configuration space for PCI Device 31: Function
0. It includes only those registers dedicated for power management. Some of the
registers are only used for Legacy Power management schemes.
404
Datasheet